I. Field of the Invention
The present invention relates to electronic circuits. More specifically, the present invention relates to logic data transfer across asynchronous clock domains.
II. Background Information
Sequential logic circuits are comprised of memory elements, such as flip flops or registers, that maintain state information, i.e., that store a value and combinational logic. The output of such memory element is a function of its inputs and of the contents, or present state of the memory element, as well. Sequential logic circuits may be characterized as either asynchronized (unclocked) or synchronized (clocked). While inputs to an asynchronous sequential logic circuit may change at any time, the inputs to a synchronous logic circuit may change the state at specific times as defined by clocking or timing methodology. As it is well-known to those having ordinary skill in the art, clocked or synchronous sequential circuits are triggered, i.e., they change state, according to clock policies input to the circuit. As the output of a memory element is a signal representing the current state of the memory element, the output of a clock sequential circuit is updated in synchronization with clock policies provided as input to the circuit.
A common timing methodology in the art is edge-trigger clocking. According to this scheme, a memory element is triggered, i.e., the one or more inputs to the memory element are sampled, during either the leading (rising) or trailing (falling) edge of a clock signal supplied as input to the memory element. For example, a trailing edge trigger flip flop changes state on the trailing edge of a clock signal in transition and maintains that state for one complete clock cycle, until another trailing edge of a clock signal is detected.
When a memory element such as a flip-flop or register is triggered by the edge of a clock signal, the input signals to the memory element need to be stable at that time. If one or more input signals to a memory element are changing state at a time at which the clock edge is received, the state and thus the output of the memory element may be unstable. When one or more inputs of a memory element are in transition at the time the memory element is triggered, thereby causing the state and output to be indeterminate, the memory element is in a metastable state. Metastability may manifest itself in many ways, including, but not limited to, an unpredictable output logic value, oscillation of the output value, indeterminate voltage level of the output representing an illegitimate logic value somewhere between a high or low logic value, and an indeterminate period of instability.
To avoid metastability, fundamental timing requirements are prescribed. One such timing requirement is "set up time" (hereinafter referred to as "T.sub.setup ") which defines that period of time immediately prior to receiving a clock edge during which inputs to the memory element need to be stable and valid. Another fundamental timing requirement, "hold time" (hereinafter referred to as "T.sub.hold "), defines that period of time immediately following reception of a clock edge during which inputs to the memory element must be stable and valid. Metastability is the resulting behavior of a synchronous element if the fundamental timing requirements are not met. Thus, each input to a synchronous element needs to be stable, i.e., a voltage level representing a valid logic value is to be maintained so that a single valid output logic value is detected for a window of time equal to T.sub.setup +T.sub.hold to avoid metastability.
When coupling two external devices together, such as digital computer and an input/output device, it may not be possible or advantageous for all the logic circuitry involved to derive a clock source from the same clock. In such a case, a plurality of clocks, each providing a clock signal to an exclusive region of the logic circuitry of a device or each providing a clock signal to the logic circuitry of separate external devices, may be employed. In such circumstances, multiple clock domains may exist. Components of a synchronous logic circuit which derive their clock source from the same clock are in the same clock domain. By contrast, components of synchronous logic circuits which derive their clock source from different independent clocks are in different clock domains.
Signals between a first synchronous logic circuit in a first clock domain and a second synchronous logic circuit in a second clock domain are transferred asynchronously. A signal transferred from the first synchronous logic circuit may be in transition at the same time a clock signal for the second synchronized logic circuit triggers the memory element that receives as input the signal from the first synchronous logic circuit. To prevent an asynchronous signal arriving at the second logic circuit from being in transition during triggering of the second logic circuit, the first and second synchronous logic circuits use control signals in the form of a two-way handshake to synchronize the asynchronously transferred signal.
However, the method of asynchronously transferring data using two-way handshake control signals limits the rate at which data may be transferred between synchronized logic circuits having different clock domains. The logic transfer across asynchronous clock domain suffers from heavy loss of performance as for each transfer across the clock domains a logic loop of change request and acknowledgement signals is generated. Consequently, each transfer incurs many additional clock cycles of performance loss. It is desired to provide a better method and apparatus for asynchronously transferring data between synchronous sequential logic circuits belonging to different clock domains.